1. Technical Field
The present invention relates to ferroelectric memory devices and electronic apparatuses equipped with the ferroelectric memory devices.
2. Related Art
Ferroelectric memories (or Ferroelectric Random Access Memory (FeRAM)) store data, using hysteresis characteristics occurring between polarization of ferroelectric material and electric fields, and are attracting attention because of their high-speed performance, low power consumption and nonvolatile property.
Each of ferroelectric memories composing a memory cell array may be formed from a ferroelectric capacitor and a transistor, wherein one end of the ferroelectric capacitor is connected to a plate line, and the other end is connected to a bit line through the transistor.
The memory cell having the structure described above may have a structure in which plugs are formed on source and drain regions of the transistor for connection to the ferroelectric capacitor and bit line. An example of related art is described in a non-patent document titled “New Development of Ferroelectric Memory” by CMC Publication on page 3.
The inventors of the present application have been in research and development of ferroelectric memory devices, and in keen examination to improve the device characteristics.
During such research and development, it has become clear that defects would likely occur in outer circumferential sections of memory cell arrays in the devices. Such defects are believed to occur because pattern density concentration and dispersion would likely occur in outer circumferential sections of memory cell arrays.
As one of the solutions to such defects, a method of disposing dummy cells (dummy transistors and dummy capacitors) in an outer circumferential area of memory cell arrays may be used. By disposing dummy cells that do not function as memory cells, the regular cell arrangement of the memory cell composing section can be secured, and the memory cell configuration can be secured, even in the outermost circumferential area of the memory cell arrays.
However, when dummy capacitors are connected to plate lines, the load on the plate lines becomes greater. Accordingly, to reduce the load, structures in which plate lines and dummy capacitors are not connected have been considered.
However, even when such a structure is adopted, it became clear that defects occurred in the outermost circumferential areas of the memory cell arrays, although the defect rate was lowered. It turned out that, because connection sections (contact sections, plugs) are not formed below (immediately below) the capacitors in the dummy cell area, the configuration of the memory cell array is not secured in the outermost circumferential area of the memory cell array, and roughness is formed in the ferroelectric films over the outermost circumferential area. This problem will be described below in greater detail.
In ferroelectric memory devices whose memory capacity is greatly affected by the orientation of ferroelectric films, the roughness formed in the films deteriorates the orientation of the films, which in turn deteriorates the memory characteristics.
In order to avoid such deficiencies, it may be possible to secure for the configuration of the connection section described above by making the dummy cells to have the same structure as that of the memory cells. However, in this case, the capacitance of the dummy capacitances described above becomes to be an additional load, which lowers the operation speed.